View ISL55112_4801574.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

High-Speed Dual Precision CCD Driver
ISL55112
The ISL55112 is a high-speed CCD array driver comprising 2 Horizontal drivers with high current output drive and 2 ancillary signal drivers with lower current output drive. The devices can be used in pairs to drive and control two halves of a high pixel count CCD array as used in high end Digital Cameras or Camcorders. The device has a largely symmetric pinout about a center axis to facilitate the placement of the devices on either side of a large CCD array with minimal signal routing disruption. The ISL55112 can accommodate split asymmetric voltage supplies up to 8V total for each of the 4 drivers and has significant flexibility in the selection of these supply voltages within this range. All 4 drivers have their own High and Low level supply lines to minimize interference between drivers caused by shared current paths. Special circuitry for the high current drivers is included to ensure the highest degree of stability of the driver output resistance over varying supply voltage, temperature and semiconductor process variations, resulting in highly consistent, predictable waveform crossover points. The ISL55112 can drive high capacitance loads at pixel clock rates exceeding 30MHz with low propagation delays, and skews between channels of better than 500ps. The ISL55112 is available in 24 Ld exposed pad TQFN package and is specified for operation over the full -40C to +85C temperature range.
ISL55112
Features
* 2 Horizontal Row Drivers (High Current) * 2 Ancillary Drivers (Lower Current) * Up to 8V Signal Swing * Unipolar and Bipolar Supply Capability * Adjustable Output Impedance for EMI Control * 3V Logic Interface * Low Propagation Delays * Low Skew: 500ps * High Clock Rates: 30MHz+ * Stand-by and Power-Down Modes
Applications*(see page 19)
* Digital Still Cameras * High Definition Digital Camcorders * Industrial Vision Systems * Medical Imaging * Semiconductor Wafer and Mask Inspection Equipment * High Definition Security Systems * Home Security Systems
Pin Configuration
ISL55112 (24 LD TQFN) TOP VIEW
RG_OUT RG_VN RG_VP
VDD 21
Ordering Information
PART NUMBER PART (Notes 1, 2, 3) MARKING ISL55112IRTZ TEMP. RANGE (C) PACKAGE PKG. (Pb-Free) DWG. #
RGIN H1IN PD ROIC EN H2IN HLIN 1 2 3 4 5 6 7
24
23
22
20 19 H1_VN 18 H1_OUT 17 H1_VP 16 DNC 15 H2_VP 14 H2_OUT 13 H2_VN
55112 IRTZ -40 to +85 24 Ld TQFN L24.4x5C
1. Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL55112. For more information on MSL please see techbrief TB363.
8 HL_VP
9 HL_OUT
10 HL_VN
11 VPLUS
12 VSUB
September 23, 2009 FN6649.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
GND
ISL55112
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME RGIN H1IN PD ROIC EN H2IN HLIN HL_VP HL_OUT HL_VN VPLUS VSUB H2_VN H2_OUT H2_VP DNC H1_VP H1_OUT H1_VN GND VDD RG_VN RG_OUT RG_VP FUNCTION Logic input for the Reset Gate (low capacitance) driver. Logic input for the H1(high capacitance) driver. Logic input for placing device in Power-Down State.This is a static input and should never be toggled above 1Hz. A resistor to VSUB, sets the output impedance of the High Current Drivers. Logic input for placing device in the enabled state. Logic input for the H2 (high capacitance) driver. Logic input for the HL Driver (low capacitance) driver. Low current driver (HL) upper supply voltage connection. Low current driver (HL) output connection. Low current driver (HL) lower supply voltage connection. Bias connection. Tie to most positive supply line on device. Bias connection. Tie to most negative supply line on device. Note: This potential is also on the exposed pad of the device. High current driver (H2) lower supply voltage connection. (Connect to same voltage as H1_VN). High current driver (H2) output connection. High current driver (H2) upper supply voltage connection. Do not connect, leave open. High current driver (H1) upper supply voltage connection. High current driver (H1) output connection. High current driver (H1) lower supply voltage connection (Connect to same voltage as H2_VN). Device ground connection. Logic supply voltage connection. Low current driver (RG) lower supply voltage connection. Low current driver (RG) output connection. Low current driver (RG) upper supply voltage connection.
2
FN6649.0 September 23, 2009
ISL55112
Functional Diagram
RG_VP RGIN RG_OUT RG_VN H1_VP H1IN OIC ADJUST . ROIC H2IN OIC ADJUST H2_VP H2_OUT H2_VN HL_VP HLIN HL_OUT HL_VN H1_OUT H1_VN
EN
PD
DEVICE POWER-DOWN
3
FN6649.0 September 23, 2009
ISL55112
Absolute Maximum Ratings
Supply Voltage (VPLUS and VSUB) . . . . . . . . . . . . . . . 9.0V Supply Voltage (H1_VP/H2_VP/RG_VP/HL_VP - H1_VN/ H2_VN/RG_VN/HL_VN) . . . . . . . . . . . . . . . . . . . . . 9.0V Supply Voltage (VDD VLOGIC) . . . . . . . . . . . . -0.3V to 6.0V Maximum Output Current H1-H2 . . . . . . . . . . . . . . 200mA Maximum Output Current RG/HL . . . . . . . . . . . . . . . 20mA Input Voltages H1/H2/RG/HL/EN/PD . . . . . (GND -0.5V) to (VLogic +0.5V) Output Voltages H1/H2//RG/HL . . . . . . . . . . . . . (VN -0.5V) to (VP +0.5V) LATCH-UP . . . . . . . . . . . . . . . . . Class II, Level A AT +85C ESD Ratings Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . 3kV Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . 300V
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 24 Ld QFN Package (Notes 4, 5) . . 37 1.5 Maximum Junction Temperature (Plastic Package). . . +150C Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature. . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features and is based on 6 Thermal Vias. See Tech Brief TB379 for details. Adding additional vias can improve thermal performance. See Tech Brief TB389. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Recommended Operating Specifications Boldface limits apply over the operating temperature range,
-40C to +85C. TEMP (C) Full Full Full Full MIN (Note 6) -2.5 -8.0 5.5 2.7 MAX (Note 6) 8.0 2.5 8.0 5.5
PARAMETER Driver Positive Supply Driver Negative Supply Driver Differential Supply Range Logic Positive Supply Voltage
SYMBOL VPn VNn VPn-VNn VDD
TEST CONDITIONS H1, H2, RG, HL H1, H2, RG, HL H1, H2, RG, HL
TYP
UNITS V V V V
NOTE: VPLUS must be connected to most positive Driver Voltage Rail, VSUB must be connected to the most negative voltage rail. VSUB should be connected to ground where Driver Negative Supplies are above ground. H1_VN and H2_VN should be connected to each other and operated at the same voltage.
Electrical Specifications
Test Conditions: XX_VP = 4V, XX_VN = -4V, VDD = 3.3V, VPLUS = 4V, VSUB = -4V, ROIC = 68k; Unless Otherwise specified. Full (-40C to +85C) limits are established by characterization and are not production tested. Boldface limits apply over the operating temperature range, -40C to +85C. TEST CONDITIONS (Note 8) TEMP (C) MIN (Note 6) TYP MAX (Note 6) UNITS
SYMBOL
PARAMETER
LOGIC INPUT CHARACTERISTICS H1/H2/RG/HL DRIVER INPUTS VIH VIL IIH IIL CIN RIN Input High Threshold Voltage H1, H2, RG, HL (Note 10) Input Low Threshold Voltage H1, H2, RG, HL (Note 10) Logic "1" Input Current H1, H2, RG, HL H1, H2, RG, HL VDD = 3.3V VDD = 3.3V VINPUT = 5.5V, VDD = 5.5V VINPUT = 0.0V, VDD = 5.5V 25 Full 25 Full 25 Full 25 Full 25 25 3.5 100k 45 30 56 2.0 2.0 1.2 1.2 63 65 175 200 V V V V A A nA nA pF
Logic "0" Input Current
Input Capacitance (Gnd) Input Resistance (Gnd)
H1, H2, RG, HL H1, H2, RG, HL
4
FN6649.0 September 23, 2009
ISL55112
Electrical Specifications
Test Conditions: XX_VP = 4V, XX_VN = -4V, VDD = 3.3V, VPLUS = 4V, VSUB = -4V, ROIC = 68k; Unless Otherwise specified. Full (-40C to +85C) limits are established by characterization and are not production tested. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) TEST CONDITIONS (Note 8) TEMP (C) MIN (Note 6) TYP MAX (Note 6) UNITS
SYMBOL
PARAMETER
LOGIC INPUT CHARACTERISTICS EN (Enable) and PD (Power-Down) DRIVER INPUT VIH VIL IIH IIL CIN RIN VOH VOL ROH ROL IPK+ Input High Threshold Voltage EN, PD (Note 11) Input Low Threshold Voltage EN, PD (Note 11) Logic "1" Input Current EN, PD VDD = 3.3V VDD = 3.3V VINPUT = 5.5V, VDD = 5.5V VINPUT = 0.0V, VDD = 5.5V 25 Full 25 Full 25 Full 25 Full 25 25 3.5 2M 3 2.0 2.0 1.2 1.2 5 5.5 45 50 V V V V A A nA nA pF
Logic "0" Input Current
EN, PD
Input Capacitance (Gnd) Input Resistance (Gnd)
EN, PD EN, PD
DRIVER SIGNAL OUTPUT CHARACTERISTICS H1 and H2 (Note 12) Driver Output High Voltage Driver Output Low Voltage Driver Source Output Resistance Driver Sink Ouput Resistance Peak Sourcing Current H1, H2: IOUT = -10mA H1, H2 IOUT = 10mA H1, H2: IOUT = -100mA (Note 12) H1, H2: IOUT = -100mA (Note 12) ROIC = 40k H1, H2: CL = 0.022f, = 68k R (Notes 12,13) OIC ROIC = 80k ROIC = 120k IPKPeak Sinking Current ROIC = 40k H1, H2: CL = 0.022f, = 68k R (Notes 12,13) OIC ROIC = 80k ROIC = 120k tR tF tPD+ tPDtSKEW+ tSKEWtSKEW Driver Rise Time H1, H2: CL = 300pF: VP = +6V, VN = -1V H1, H2: CL = 300pF: VP = +6V, VN = -1V H1, H2: CL = 300pF: VP= +6V, VN = -1V H1, H2: CL = 300pF: VP= +6V, VN = -1V H1, H2: CL = 300pF 25 25 25 25 25 25 25 25 25 25 25 25 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full -0.50 -0.50 0 0.50 -0.50 0 0.50 0 0.50 7.7 7.7 2.8 3.9 -3.95 3.93 -3.93 2.8 2.0 2.66 2.04 1.96 1.66 2.18 1.72 1.64 1.52 2.8 4.2 4.3 4.2 4.3 10.1 10.5 10.1 10.5 3.95 -3.90 9 8 V V ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Driver Fall Time
Propagation Delay Rising Edge Propagation Delay Falling Edge Driver Skew, H1 to H2 Rising Edge
Driver Skew, H1 to H2 Falling H1, H2: CL = 300pF Edge Skew: H1 Rising H2 Falling H1, H2: CL = 300pF
5
FN6649.0 September 23, 2009
ISL55112
Electrical Specifications
Test Conditions: XX_VP = 4V, XX_VN = -4V, VDD = 3.3V, VPLUS = 4V, VSUB = -4V, ROIC = 68k; Unless Otherwise specified. Full (-40C to +85C) limits are established by characterization and are not production tested. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) TEST CONDITIONS (Note 8) H1, H2: CL = 300pF H1, H2: CL = 300pF: VP= +6V, VN = -1V H1, H2: CL = 300pF CHINT tMIN tMIN VOH VOL ROH ROL tR tF tPD+ tPDtSKEW+ tSKEWFMAX Calculated Empirical Internal H1, H2: H Driver capacitance CL = 0 Min Pulse Width Min Pulse Width CL = 0pF CL = 300pF VP = 6, VN = -1V RG, HL: IOUT = -1mA RG, HL; IOUT = 1mA RG, HL: IOUT = -10mA RG, HL: IOUT = -10mA RG, HL: CL = 22pF RG, HL: CL = 22pF RG, HL: CL = 22pF (Note 14) RG, HL: CL = 22pF (Note 14) RG, HL: CL = 22pF, ROIC = 40k ROIC = 120k 40MHz, ROIC = 68k TEMP (C) 25 Full FMAX Max Operating Frequency 25 25 25 25 25 25 4 -0.50 40 70 55 60 2.5 5.5 8 MIN (Note 6) TYP 0 0.50 MAX (Note 6) UNITS ns ns MHz MHz MHz pF ns ns
SYMBOL tSKEW
PARAMETER Skew: H2 Rising H1 Falling
DRIVER SIGNAL OUTPUT CHARACTERISTICS RG and HL Driver Output High Voltage Driver Output Low Voltage Driver Source Output Resistance Driver Sink Ouput Resistance Driver Rise Time 25 25 25 Full 25 Full 25 Full Driver Fall Time 25 Full Propagation Delay Rising Edge Propagation Delay Falling Edge Driver Skew, RG to HL Rising Edge 25 Full 25 Full 25 Full 25 Full 25 Full 25 25 -0.5 40 60 3.6 6.5 -0.5 0 0.50 7.9 0 0.50 7 8.5 9.0 3.1 7.6 8.2 2.5 3.4 3.7 3 3.5 17 3.96 -3.99 3.97 -3.97 22 3.99 -3.96 55 56 55 56 V V ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns
Driver Skew, RG to HL Falling RG, HL: CL = 22pF, Edge Max Operating Frequency RG. HL: CL = 90pF: VP = +6V, VN = -1V RG, HL: CL = 22pF CL = 0pF CL = 22pF Time VDD Current Drops to < 100A (Note 8) Time H-Drivers tPD/tR/tF Takes to Stabilize (Note 8)
tMIN tMIN tPD ON tPD OFF
Min Pulse Width Min Pulse Width
Power Down and Driver Enable timing (Note 8) Active Mode to Power Down Time Power Down to Active Mode Time 25 25 25 25 50 50 s s
6
FN6649.0 September 23, 2009
ISL55112
Electrical Specifications
Test Conditions: XX_VP = 4V, XX_VN = -4V, VDD = 3.3V, VPLUS = 4V, VSUB = -4V, ROIC = 68k; Unless Otherwise specified. Full (-40C to +85C) limits are established by characterization and are not production tested. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) TEST CONDITIONS (Note 8) CLK Running at 30MHz TEMP (C) 25 25 MIN (Note 6) TYP 33 33 MAX (Note 6) UNITS ns ns
SYMBOL tEN ON tEN OFF
PARAMETER Driver Enable to Disable Mode Time Drivers Disable to Enable Mode Time
Standby Supply Current: EN = 1:PD = 0 ISB Current on each pin type, Input= = 0Hz H1_VP, H2_VP H1_VN, H2_VN RG_VP, HL_VP RG_VN, HL_VN VDD VPLUS VSUB Power-Down Supply Current: EN = X, PD =1 IPD Current on each pin type H1_VP, H2_VP H1_VN, H2_VN RG_VP, HL_VP RG_VN, HL_VN VDD VPLUS VSUB +4.0V 25 Full -4.0V 25 Full +4.0V 25 Full -4.0V 25 Full 3.3V 25 Full +4.0V 25 Full -4.0V 25 Full -400 -450 -70 70 -200 -250 30 300 320 400 450 -10 -450 -500 10 200 250 -70 70 450 500 A A A A A A A A A A A A A A +4.0V 25 Full -4.0V 25 Full +4.0V 25 Full -4.0V 25 Full 3.3V 25 Full +4.0V 25 Full -4.0V 25 Full -2.2 -2.5 -1.4 1.0 -1.5 -1.7 .75 1.2 1.3 1.8 2.0 -0.25 -5 -5.5 0.25 1.5 1.7 -2.5 2.5 4.75 5 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
7
FN6649.0 September 23, 2009
ISL55112
Electrical Specifications
Test Conditions: XX_VP = 4V, XX_VN = -4V, VDD = 3.3V, VPLUS = 4V, VSUB = -4V, ROIC = 68k; Unless Otherwise specified. Full (-40C to +85C) limits are established by characterization and are not production tested. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) TEST CONDITIONS (Note 8) TEMP (C) MIN (Note 6) TYP MAX (Note 6) UNITS
SYMBOL
PARAMETER
Active Supply Current: EN=1, PD=0 IACT Current on each pin type; 40 MHz input: Note 15 H1_VP, H2_VP H1_VN, H2_VN RG_VP, HL_VP RG_VN, HL_VN VDD VPLUS VSUB NOTES: 6. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Full Temperature limits established by characterization and are not production tested. 7. The algebraic convention, where by the most negative value is the minimum and the most positive a maximum, is used in the data sheet. 8. All load capacitances are with respect to Gnd. 9. PD (Power-Down) is a static control. Do not allow toggle frequency above 1 Hz. PD should be used in combination with EN pin during Active and Inactive state changes. (See Power Mode Sequencing). 10. H1, H2, EN, RG, HL VIH and VIL Thresholds established while toggling @10MHz. 11. PD VIH and VIL Thresholds established while toggling @ 1Hz. 12. ATE test conditions limit rON measurement capability. Refer to Characterization tables for typical rON Values. The Output Impedance Control active circuitry adjusts rON characteristics dynamically. 13. Peak current as measured with evaluation board with 1 resistor in series with 0.022F capacitor. Measurements as characterized with ISL55112 Evaluation board. 14. Dynamic FULL/MIN/MAX data recorded with ISL55112 Evaluation board. Series inductance of decoupling, loads and interconnect will greatly influence this measurement. See section on "Power Supply Bypassing and Printed Circuit Board Layout" on page 11. 15. As measured using evaluation board with H1_OUT, H2_OUT = 300pF load on each output and RG_OUT, HL_OUT = 22pF load on each output. +4.0V -4.0V +4.0V -4.0V 3.3V, All driver inputs running +4.0V -4.0V 25 25 25 25 25 25 25 118 -118 15 -15 3.8 0.9 -0.9 mA mA mA mA mA mA mA
Test Circuits and Waveforms
3V IN VDD EN IN OUT CL OUT SIGNAL GENERATOR OUT tPD+ 50% tPDVP 50% VN 90% 10% tR 90% 10% tF VP VN 50% 50% 0V
FIGURE 1A. TEST CIRCUIT
FIGURE 1B. MEASUREMENT POINTS
FIGURE 1. DRIVER PROPAGATION DELAY AND RISE AND FALL TIMES
8
FN6649.0 September 23, 2009
ISL55112
Test Circuits and Waveforms (Continued)
EN IN SIGNAL GENERATOR SIGNAL GENERATOR OUT OUT CL EN 50% tEN ON 50% 50% VN VP OUT 50% 50% VN 50% 0V tEN OFF VP 3V
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. DRIVER ENABLE AND DISABLE TIMES
1000pF AND 0.1F VDD = 3.3V XX_VP = 4V XX_VN = -4V GND = 0V 22pF
1000pF AND 0.1F RGOUT RG_VN RG_VP
0.1F AND 4.7F
VDD 21
24 RGIN H1IN 1 2 3 4 5 6 7 8 HL_VP
23
22
GND 20 19 18 17 H1_VN H1OUT H1_VP 300pF 16 NC 15 14 13 H2_VP H2OUT H2_VN 300pF 12 VSUB
PD should not be operated above 1Hz
PD 68k ROIC EN H2IN HLIN
9 HLOUT
10 HL_VN
11 VPLUS
ALL CAPACITORS ABOVE ARE 0.1F AND BULK DECOUPLING CAPACITORS (NOT SHOWN) ON EACH SUPPLY 0.1F
1000pF AND 0.1F 0.1F
22pF
1000pF AND 0.1F
0.1F
FIGURE 3. STANDARD TEST CONFIGURATION
9
FN6649.0 September 23, 2009
ISL55112
RG_VP RG_VN 3.3V 24 23 22 21 20 RGOUT CCD Array with Dual Video Outputs RGOUT RG_VN RG_VP
PIN 12 (VSUB)
RGIN 1 H1IN 2 3 4 5 H2IN 6 HLIN 7
19 18 H1OUT 17 HXVP 15 14 H2OUT 13
H1OUT HXVP H2OUT
13 14 15 17 18 19
12 11 10 9 8 7 6 5 4 3 2 1
RGIN H1IN
PIN 12 (VSUB) H2IN HLIN
8 9 10 11 12
HLOUT
HLOUT 3.3V
HL_VP
HL_VN
HL_VN
20 21 22 23 24 HL_VP
FIGURE 4. SYMMETRY ACCOMMODATES DUAL DEVICE UTILIZATION WITH A DUAL VIDEO CCD DEVICE
Application Information
The ISL55112 2+2 CCD device provides four drivers for horizontal inputs of CCD arrays. It comprises two high capacitance drivers (H1/H2) and two low capacitive drivers for handling Reset Gate (RG)/Last H (HL) inputs of a CCD device. From an applications and physical routing standpoint, the H1/H2 (high current drivers) have identical circuitry. Likewise, the HL/RG (low current drivers) circuitry is the same internally. In dual device applications, the user is free to swap driver outputs to accommodate layout requirements. The ISL55112 H1/H2 have fast rise / fall times into large capacitive loads. H1/H2 are designed with short propagation delays and tightly controlled skew, allowing the device to be used on large, fast CCD arrays, used in image processing applications
CCD Driver Rails
Each of the four driver outputs has its own set of high and low rail supply connections. The positive rail connections for the drivers are RG_VP, HL_VP, H1_VP, H2_VP. The negative driver rail connections are RG_VN, HL_VN, H1_VN, H2_VN. (Note H1_VN = H2_VN and should always be at the same voltage). Once the user has defined the "Driver" amplitudes required by the CCD, Device bias connections, VPLUS and VSUB must be connected to the maximum and minimum voltage required.
Device Bias connections
VPLUS should be connected to the most positive voltage. VSUB should be connected to the most negative voltage. Accordingly, the VPLUS/ VSUB connections can only be determined once the CCD device driver output amplitude requirements have been determined.
Supply Voltages
The ISL55112 has three types of pins when it comes to supply voltages: Logic, driver rails and device bias connections.
Dual Video CCD Connection Considerations
Physical placement that keeps series inductance to a minimum is important. The ISL55112 design accommodates dual device placement close to a CCD device. H1 / H2 and RG / HL drivers are internally identical. The user can rotate the device for PCB placement close to a single CCD with dual-video requirements.
VDD and Ground Supply Connections
The ISL55112 has a logic supply (VDD) that can be set from 2.7V to 5.5V. Hence the VDD supply voltage sets the operating thresholds for the digital inputs H1IN, H2IN, RGIN, HLIN, and EN pins are high speed digital logic connections. Typically they are logic connections coming from the master CCD timing generator. PD should have fast transitions, but should not run at frequencies above 1Hz.
Power Supply Sequencing
The ISL55112 substrate is connected to the VSUB Pin. Positive Protection is connected to the VPLUS pin. The system supply GND connection will always be present, and is the reference to all other supply voltages. Therefore apply VDD, VPLUS, VSUB followed by the VP, VN busses. Digital inputs should be driven as soon as all
10
FN6649.0 September 23, 2009
ISL55112
power inputs have settled but should not be allowed to float during power-up and power-down operations. Note: If VSUB floats high when VDD is applied, a 10k to 50k Resistor should be added from VSUB to ground. For proper power up biasing, VSUB should not be allowed to float high when only VDD is applied. (C1, C4, C6, C11). Figure 6 shows vias between bottom decoupling and the device pins on top increase series inductance. However, bottom decoupling replenishes the top decoupling before and after edge currents occur. Additional bulk decoupling (22F to 4.7F) should also be used. This is low frequency decoupling and need not be located as close to the output area of the device.
Power Supply Bypassing and Printed Circuit Board Layout
Maximum current occurs during edge-transition of the driver outputs. Decoupling of the VP and VN rails for the drivers is of paramount concern. This being especially true of the high current drivers. Minimum possible lead length from the VP/VN device connections to the associated decoupling capacitors is key to device performance. Given transition times are the point of maximum current, series inductance from the decoupling point to the VP/ VN connections and from the VOUT connection to the CCD should be kept to the minimum possible values. Note: The ISL55112 employs multiple bond wires on all driver rail and driver output connections. Multiple bond wires help reduce the device package internal bond wire connection inductance. As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. The "Evaluation Board" drawing depicts a conceptual decoupling scenario. Capacitor values, placement and quantities are subject to specific application requirements. The key to decoupling, especially during edge transitions, is to reduce the series inductance of the VP/VN supply rails.
FIGURE 5. TOP COMPONENT AND PCB ARTWORK
Decoupling Discussion and Evaluation Board Information
* With split supply driver voltages, each VN and VP pin should have a separate 0.1F capacitor to ground. The capacitors should be on the top layer of the PCB to a ground plane. This avoids the operative decoupling point having a via in series with the device pin. * Single supply applications require fewer decoupling capacitors (VN rails are connected to ground. In this case, the top layer should also be a ground plane and VP pins should be decoupled as closely as possible. * In both cases, the return path series inductance needs to be considered. The return current path of the load and the decoupled point should be as close as possible. Avoid/reduce Vias between driver rail decoupling points and driver output to load. Figure 5 shows the top decoupling provides the high frequency driver rail decoupling during edge transitions 11
FIGURE 6. BOTTOM COMPONENT AND PCB ARTWORK
Output Impedance Control (OIC)
An external Resistor, ROIC, is used to set the output impedance of the high current drivers. Selection of ROIC resistance value enables the user to adjust high current H1/H2 driver operation for a specific CCD product. Rise and Fall times can be adjusted via the ROIC resistance setting. This is accomplished by selecting an ROIC resistance value from 40k to 120k. Actual rise/fall timing will be the product of driver loading and interconnect parasitics. High current driver characteristics, which are normally affected by temperature and process variations, are kept to a minimum by the ISL55112 OIC feature.
FN6649.0 September 23, 2009
ISL55112
Dynamic Measurements
The ISL55112 drivers require minimum series inductance to operate properly. Therefore it is not recommended that test sockets be used when evaluating driver performance. Parts should be soldered to an appropriate layout that addresses both driver load and driver rail decoupling series inductance. When EN is set to the active state (High), the drivers will respond to driver inputs. Reaction time to the 1st drive pulse is defined in the electrical table as "tEN ON" on page 7. During initial Power-Up, H1 and H2 Outputs will be HIz until a transition occurs on the H1 and H2 Inputs.
Input Signals
The ISL55112 has logic signal inputs on H1,H2, RG and HL drivers. The ISL55112 also has two "mode control" pins (PD and EN) which enable the user to control power requirements. Input signals switching thresholds are set by the VDD to Gnd voltage.
Device Power-Down (PD)
In Power-Down Mode, both input circuitry and gate drive circuitry is powered down. Power-down should only be used for static control. Do not exceed 1Hz of operation. The recommended sequences for Power Mode control are: MODE CONTROL POWER-DOWN SEQUENCE Device active (Enable High, Power Down Low) * Set Power Down High Set Enable Low. MODE CONTROL POWER-UP SEQUENCE Device inactive (Enable Low, Power Down High) * Set Enable High, Set Power Down Low
Power Saving Mode Control
The ISL55112 offers two methods of power reduction. The Power Down control pin is to be used in conjunction with Enable pin. (See "Mode control Power-Down sequence" and "Mode control Power-Up sequence" on page 12).
Driver Standby (EN)
(EN: Low, PD Low) In this state the gate drive circuit is active but the front end receivers are shut off. Shorter term power savings can be realized by using the EN input. When EN is disabled (EN: Low, PD: Low), the driver outputs will stay in their last state prior to setting the EN signal low. The "tEN off" specification indicates the response time for the drivers to hold their present logic state.
Power Dissipation Considerations
Specifying continuous data rates, driver loads and driver level amplitudes are key in determining power supply requirements as well as dissipation/cooling necessities. Driver Output patterns also impact these needs. The faster the pin activity, the greater the need to supply current and remove heat.
TABLE 1. ISL55112 DETAILED POWER DISSIPATION FORMULA/EXAMPLE FORMULA VARIABLE VDD H_Diff HL_Dif RG_Diff H1_Freq H2_Freq HL_Freq RG_Freq Driver Loads H1_CLOAD H2_CLOAD HL_CLOAD RG_CLOAD Default Currents IDD 1 mA Stand By VDD Current 300 300 20 20 pF pF pF pF High Capacitance Load High Capacitance Load Low Capacitance Load Low Capacitance Load EXAMPLE VALUES 3.3 8 8 8 40 40 40 40 UNIT V V V V MHz MHz MHz MHz VARIABLES SQUARED VDD2 H_Diff2 HL_Diff2 RG_Diff2 Operating Frequency Operating Frequency Operating Frequency Operating Frequency CALCULATIONS 10.89 64 64 64 VDD2 Hx_VP - Hx_VN HL_VP-HL_VN RG_VP-RG_VN NOTES
POWER DISSIPATION FORMULA ISL55112: OPERATION VARIABLES
POWER DISSIPATION FORMULA ISL55112: DEVICE VARIABLES
12
FN6649.0 September 23, 2009
ISL55112
TABLE 1. ISL55112 DETAILED POWER DISSIPATION FORMULA/EXAMPLE (Continued) FORMULA VARIABLE IH Log_Cint H1_Cint H2_Cint HL_Cint RG_Cint EXAMPLE VALUES 6 3.5 60 60 6.3 6.3 UNIT mA pF pF pF pF pF VARIABLES SQUARED CALCULATIONS NOTES
Stand By IH Current Per channel internal logic switching load Effective Internal Driver Capacitance Effective Internal Driver Capacitance Effective Internal Driver Capacitance Effective Internal Driver Capacitance Example Calculation
Device Internal Capacitance
POWER DISSIPATION FORMULAS AND EXAMPLE CALCULATIONS Wattage Sub Totals and Formula Standby Watts H1_Logic_Watts H2_Logic_Watts HL_Logic_Watts RG_Logic_Watts H1_Cint_Watts H2_Cint_Watts HL_Cint_Watts RG_Cint_Watts H1_Cload_Watts H2_Cload_Watts HL_Cload_Watts RG_Cload_Watts Total Watts TJA 37 = = = = = = = = = = = = = VDD*IDD + H_DIFF*IH Log_Cint*VDD2 * H1_Freq Log_Cint*VDD2 * H2_Freq Log_Cint*VDD2 * HL_Freq Log_Cint*VDD2 * RG_Freq H1_Cint*H_Diff2 * H1_Freq H2_Cint*H_Diff2 * H2_Freq HL_Cint*HL_Diff2 * HL_Freq RG_Cint*RG_Diff2 * RG_Freq H1_Cload*H_Diff2 * H1_Freq H2_Cload*H_Diff2 * H2_Freq HL_Cload*HL_Diff2 * HL_Freq RG_Cload*RG_Diff2 * RG_Freq Total Watts Degrees over ambient 0.0513 0.0015 0.0015 0.0015 0.0015 0.1536 0.1536 0.0161 0.0161 0.7680 0.7680 0.0563 0.0563 2.0455 75.68
Power Dissipation Notes
Power dissipation consists of 4 contributors: 1. Contributor 1 corresponds to the Standby Current of the VDD Logic Supply (IDD) and VP-VN Driver Rails (IH) 2. Contributor 2 corresponds to the dissipation from running the H1, H2, RG and HL Inputs. Log_Cint specifies the basis for the power consumed from the VDD Supply for each input. 3. Contributor 3 corresponds to the Driver Rail Supply dissipation due to internal capacitance. The value of H1_Cint, H2_Cint, RG_Cint and HL_Cint correspond to the effective internal capacitance of the drivers. 4. Contributor 4 corresponds to the Driver Rail Supply dissipation due to load capacitance. The value of H1_Cload, H2_Cload, RG_Cload and HL_Cload correspond to the external capacitance of the device being driven. These are approximate formulae and the actual values may be 15% to 20% off.
The maximum power dissipation allowed in a package is determined according to Equation 1:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA (EQ. 1)
where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads. Power also depends on number of channels changing state and the frequency of operation. The reader is cautioned against assuming the same level of thermal performance in actual applications. A careful inspection of conditions in your application should be conducted. Great care must be taken to ensure Die Temperature does not exceed +150C Absolute Maximum Thermal Limits.
13
FN6649.0 September 23, 2009
ISL55112
Important Note: The ISL55112 exposed pad is used for heat sinking of the device. It must be electrically connected to the most negative supply potential needed for driver output (VSUB). Therefore, when negative drive rails are used, the thermal pad (VSUB) must be isolated from ground.
Typical Performance Curves
VDD = 3.3V, VH = 4V, VN = -4V, ROIC = 68k, CL= 300pF for H1/2OUT, CL = 22pF for RG/HLOUT, Unless specified otherwise. Refer to Figures 1, 2 and 3. (Information derived from ISL55112 Evaluation board characterization. See AN1495 ISL55112 Evaluation Board).
2.5
3.4 IOUT = -100mA 3.2 +85C 3.0 rON () +25C 2.8 2.6 2.4 2.2 rON ()
2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 -40C +85C
IOUT= +100mA
+25C
-40C
4
5
6 VH, DRIVE RAIL (V)
7
8
1.5
4
5
6 7 VH, DRIVE RAIL (V)
8
FIGURE 7. H1/H2 DRIVER SOURCE RESISTANCE vs VH
29 28 27 26 rON () 25 24 23 22 21 20 19 4.5 -40C 5.5 6.5 VH, DRIVE RAIL (V) 7.5 8.0 +25C +85C IOUT = -10mA
FIGURE 8. H1/H2 DRIVER SINK RESISTANCE VS VH
20 +85C 19 18
IOUT = +10mA
rON ()
17 +25C 16 15 14
-40C 4.5 5.5 6.5 VH, DRIVE RAIL (V) 7.5 8.0
FIGURE 9. RG/HL DRIVER SOURCE RESISTANCE vs VH
FIGURE 10. RG/HL DRIVER SINK RESISTANCE vs VH
14
FN6649.0 September 23, 2009
ISL55112
Typical Performance Curves
VDD = 3.3V, VH = 4V, VN = -4V, ROIC = 68k, CL= 300pF for H1/2OUT, CL = 22pF for RG/HLOUT, Unless specified otherwise. Refer to Figures 1, 2 and 3. (Information derived from ISL55112 Evaluation board characterization. See AN1495 ISL55112 Evaluation Board).
2.15
2.9 2.8 2.7 rON () 2.6 ROIC = 68k 2.5 2.4 ROIC = 40k 2.3 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 rON () ROIC = 120k ROIC = 80k
VH 8V IOUT = -100mA
2.10 2.05
ROIC = 120k
VH 8V IOUT = +100mA
ROIC = 80k 2.00 1.95 1.90 1.85 2.5 ROIC = 68k
ROIC = 40k
3.0
3.5
4.0 VDD (V)
4.5
5.0
5.5
FIGURE 11. H1/H2 SOURCE RESISTANCE vs VDD
FIGURE 12. H1/H2 SINK RESISTANCE vs VDD
950 930 910 890 IDD (A) 870 850 830 810 790 770 750 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 +85C TO -40C
3.10 3.05 RISE/FALL TIME (ns) 3.00 2.95 2.90 2.85 2.80 2.5 RISE FALL
3.0
3.5
4.0 VDD (V)
4.5
5.0
5.5
FIGURE 13. STAND BY CURRENT (Isb) IDD vs VDD
9.0 8.5 RISE/FALL TIME (ns) 8.0 7.5 IH (mA) 7.0 6.5 6.0 5.5 5.0 4.5 4.0 4.5 5.5 6.5 VH, DRIVE RAIL (V) 7.5 8.0 +25C -40C +85C
FIGURE 14. H1/H2 RISE AND FALL vs VDD
3.7 3.5 3.3 FALL 3.1 2.9 RISE 2.7 2.5 2.5
3.0
3.5
4.0 VDD (V)
4.5
5.0
5.5
FIGURE 15. STAND BY CURRENT (Isb) IH vs VH
FIGURE 16. RG/HL RISE AND FALL vs VDD
15
FN6649.0 September 23, 2009
ISL55112
Typical Performance Curves
VDD = 3.3V, VH = 4V, VN = -4V, ROIC = 68k, CL= 300pF for H1/2OUT, CL = 22pF for RG/HLOUT, Unless specified otherwise. Refer to Figures 1, 2 and 3. (Information derived from ISL55112 Evaluation board characterization. See AN1495 ISL55112 Evaluation Board).
600
8 7 6 IDD (mA) IH (mA) 5 4 3 2 1 0 0M 20M 40M 60M 80M TOGGLE FREQUENCY (Hz) 100M110M CL = 300pF, 22pF CL = OPEN
500 400 CL = 300pF, 22pF 300 200 CL = OPEN 100 0 0M
20M
40M 60M 80M TOGGLE FREQUENCY (Hz)
100M110M
FIGURE 17. IDD vs FREQUENCY (ALL OUTPUTS ACTIVE)
3.0 2.8 2.6 2.4 LOGIC (V) 2.2 2.0 1.8 1.6 1.4 1.2 1.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 +85C OR -40C +25C
FIGURE 18. IH vs FREQUENCY (ALL OUTPUTS ACTIVE)
2.6 2.4 2.2 LOGIC (V) 2.0 1.8 1.6 1.4 1.2 +85C OR -40C 1.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 +25C
FIGURE 19. ALL INPUTS VIH LOGIC THRESHOLDS
FIGURE 20. ALL INPUTS VIL LOGIC THRESHOLDS
14 13 12 11 10 9 8 7 6 5 4 CL = 300pF 3 2 CL = 122pF 1 0 40 50 60 70 80 90 ROIC (k)
13 12 11 CL = 1000pF FALL TIME (ns) 10 9 8 7 6 5 4 3 2 1 120 0 40 50 60 70 80 90 ROIC (k) CL = 122pF CL = 0pF 100 110 120 CL = 300pF CL = 50 CL = 680pF CL = 1000pF
RISE TIME (ns)
CL = 680pF
CL = 50 CL = 0pF 100 110
FIGURE 21. H1/H2 tr vs ROIC vs CL
FIGURE 22. H1/H2 tf vs ROIC vs CL
16
FN6649.0 September 23, 2009
ISL55112
Typical Performance Curves
VDD = 3.3V, VH = 4V, VN = -4V, ROIC = 68k, CL= 300pF for H1/2OUT, CL = 22pF for RG/HLOUT, Unless specified otherwise. Refer to Figures 1, 2 and 3. (Information derived from ISL55112 Evaluation board characterization. See AN1495 ISL55112 Evaluation Board).
12.0 11.5 PROPAGATION DELAY (ns) 11.0 10.5 10.0 9.5 tpd , C = 680pF f L 9.0 8.5 8.0 7.5 tpdf, CL = 300pF tpdr, CL = 680pF tpdf, CL = 1000pF tpdr, CL = 1000pF
7.0 6.8 PROPAGATION DELAY (ns) 6.6 tpdf, CL = 122pF 6.4 6.2 6.0 5.8 5.6 5.4 5.2 5.0 -40 -20 0 20 40 60 80 tpdf, CL = 50 tpdr, CL = 50 tpdr, CL = 122pF
tpdr, CL = 300pF 20 40 60 80
7.0 -40
-20
0
PACKAGE TEMP (C)
PACKAGE TEMP (C)
FIGURE 23. H1/H2 tpdr/f vs TEMPERATURE vs CL
9 8 RISE TIME (ns) 7 6 5 4 3 2 +85C +25C
FIGURE 24. H1/H2 tpdr/f vs TEMPERATURE vs CL
12 11 10 FALL TIME (ns) 9 8 7 6 5 4 +25C -40C +85C
-40C
20
30
40
50
60 70 CL (pF)
80
90
100
3 20
30
40
50
60 70 CL (pF)
80
90
100
FIGURE 25. RG/HL tr vs CL
FIGURE 26. RG/HL tf vs CL
11.0 PROPAGATION DELAY (ns) 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 20 30 40 50 60 CL (pF) 70 80 90 100 -40C +85C +25C TIME (ns)
2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3
CL = 122pF tf
tr
1.2 40
50
60
70
80
90
100
110
120
ROIC (k)
FIGURE 27. RG/HL tpdr vs CL
FIGURE 28. H1/H2 tr/f vs ROIC
17
FN6649.0 September 23, 2009
ISL55112
Typical Performance Curves
VDD = 3.3V, VH = 4V, VN = -4V, ROIC = 68k, CL= 300pF for H1/2OUT, CL = 22pF for RG/HLOUT, Unless specified otherwise. Refer to Figures 1, 2 and 3. (Information derived from ISL55112 Evaluation board characterization. See AN1495 ISL55112 Evaluation Board).
3.4 3.3 RISE & FALL TIME (ns) 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.4 -40 -20 0 20 40 PACKAGE TEMP (C) 60 80 H1 tr H1 tf
Die Characteristics
SUBSTRATE AND TQFN THERMAL PAD POTENTIAL (POWERED UP): VSUB TRANSISTOR COUNT: 3900 PROCESS: SUB MICRON CMOS
FIGURE 29. H1 tr / tf vs TEMPERATURE
TQFN Package Discussion
Typically, power dissipation is a limiting factor in CCD array driving applications. The key tool in removing heat from the drivers is the thermal pad on the bottom of the TQFN package. Electrically, this exposed pad is connected to the device substrate and is the most negative voltage. In applications where negative drive rails are used, this pad must be isolated from ground and connected to the negative bus. However, the size of the thermal pad and the associated voltage plane/layer it connects to determines the heat dissipation capability of the pad.
The footprint for the ISL55112 should include a "Thermal Via Array" of through-holes. Hole size and spacing of these vias should maximize heat transfer to the bottom of the board and away from the device. Hole size should accommodate solder wicking requirements. The quantity of vias is limited by pad size and recommended spacing. Vias should also have a solid connection to the associated power plane. Another item that affects thermal transfer is the layout on the bottom of the board. Circuit lands that run parallel with the package can actually become heat barriers. If signals are routed on the bottom, try to route signal paths (90) away from the pad area. Make the exposed pad area as large as possible on the bottom layer. (Remember in negative voltage applications the pad needs to be electrically isolated from the ground plane.) Reference Intersil TB-389 A grid of 1.0mm to 1.2mm pitch thermal vias, which drop down and connect to buried copper plane(s), should be placed under the thermal land. The vias should be about 0.3mm to 0.33mm in diameter, with the barrel plated to about 1.0 ounce copper. Although adding more vias (such as by decreasing via pitch) will improve thermal performance, diminishing returns will be seen as more and more vias are added. Therefore, simply use as many vias as practical for the thermal land size and your board design ground rules.
TOP VIEW
BOTTOM VIEW
The TQFN Thermal Pad is the main tool for dealing with Power Dissipation.
FIGURE 30. ISL55112 TQFN PAD LAYOUT EXAMPLE TOP AND BOTTOM VIEWS
Recommended Land Pattern (TQFN PCB Footprint)
Please refer to the Package Outline Drawing for recommended land size guidelines.
18
FN6649.0 September 23, 2009
ISL55112
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 9/23/09 REVISION FN6649.0 Initial Release. CHANGE
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL55112 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 19
FN6649.0 September 23, 2009
ISL55112
Package Outline Drawing
L24.4x5C
24 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 10/07
PIN 1 INDEX AREA 6 B 20 24 4.00 A 24X0.40 2.65 PIN #1 INDEX AREA CHAMFER 0.400 X 45 x 6 1 0.50 5.00 3.65
19
0.5x6=3.00 REF
13
7
0.10
12 0.50
8 0.230.05 0.10 M C A B
4X
TOP VIEW
0.5x4=2.00 REF BOTTOM VIEW
SEE DETAIL X'' 0.10 C C 0.75 (24x0.25) SIDE VIEW (4.80 TYP) (3.65) SEATING PLANE 0.08 C
(20x0.50) 5
0 . 20 REF
(24x0.60) C
(2.65) (3.80 TYP)
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.28mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1
20
FN6649.0 September 23, 2009

▲Up To Search▲

Price & Availability of ISL55112

	To Download ISL55112 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .